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NB2305A 3.3 V Zero Delay Clock Buffer
The NB2305A is a versatile, 3.3 V zero delay buffer designed to distribute high-speed clocks. It accepts one reference input and drives out five low-skew clocks. It is available in a 8 pin package. The -1H version of the NB2305A operates at up to 133 MHz, and has higher drive than the -1 devices. All parts have on-chip PLL's that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. Multiple NB2305A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. The NB2305A is available in two different configurations, as shown in the ordering information table. The NB2305A1 is the base part. The NB2305Ax1H* is the high drive version of the -1 and its rise and fall times are much faster than -1 part.
Features http://onsemi.com MARKING DIAGRAMS*
8 1 SOIC-8 D SUFFIX CASE 751 1 8 XXXX ALYW G
8 8 1 TSSOP-8 DT SUFFIX CASE 948J XXX ALYWG G 1
* 15 MHz to 133 MHz Operating Range, Compatible with CPU and * * * * * * * * *
PCI Bus Frequencies Zero Input - Output Propagation Delay Multiple Low-Skew Outputs Output-Output Skew Less than 250 ps Device-Device Skew Less than 700 ps One Input Drives 5 Outputs Less than 200 ps Cycle-to-Cycle Jitter is Compatible with PentiumR Based Systems Available in 8 Pin, 150 mil SOIC Package and 8 Pin TSSOP 4.4 mm 3.3 V Operation, Advanced 0.35 m CMOS Technology These are Pb-Free Devices
XXXX = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
*x = C for Commercial; I for Industrial.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 5
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Publication Order Number: NB2305A/D
NB2305A
REF
PLL
CLKOUT REF CLK2 CLK2 CLK1 CLK3 GND 3 4 1 2 8 7 CLKOUT CLK4 VDD CLK3
CLK1
NB2305A
6 5
CLK4
Figure 1. Block Diagram
Figure 2. Pin Configuration
Table 1. PIN DESCRIPTION
Pin # Pin Name Description
1 2 3 4 5 6 7 8
REF (Note1) CLK2 (Note 2) CLK1 (Note 2) GND CLK3 (Note 2) VDD CLK4 (Note 2) CLKOUT (Note 2)
Input reference frequency, 5 V tolerant input. Buffered clock output. Buffered clock output. Ground. Buffered clock output. 3.3 V supply. Buffered clock output. Buffered clock output, internal feedback on this pin.
1. Weak pulldown. 2. Weak pulldown on all outputs.
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NB2305A
Table 2. MAXIMUM RATINGS
Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Maximum Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 >2000 Unit V V V C C C V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
Table 3. OPERATING CONDITIONS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Commercial Industrial Description Min 3.0 0 -40 Max 3.6 70 85 30 10 7 Unit V C pF pF pF
Table 4. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter VIL VIH IIL IIH VOL VOH IDD IDD Description Input LOW Voltage (Note 3) Input HIGH Voltage (Note 3) Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current (Commercial Temp) Supply Current (Industrial Temp) VIN = 0 V VIN = VDD IOL = 8 mA (-1) IOL = 12 mA (-1H) IOH = -8 mA (-1) IOH = -12 mA (-1H) Unloaded outputs at 66.67 MHz, Select inputs at VDD 100 MHz 66.67 MHz 33 MHz Select inputs at VDD or GND, at Room Temp Unloaded outputs at 2.4 34 50 34 19 2.0 50 100 0.4 Test Conditions Min Max 0.8 Unit V V mA mA V V mA mA
3. REF input has a threshold voltage of VDD/2.
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NB2305A
Table 5. SWITCHING CHARACTERISTICS (Commercial and Industrial) (Note 4)
Parameter 1/t1 1/t1 t3 t4 t5 t6 t7 tJ tLOCK trin tfin Description Output Frequency Duty Cycle = (t2 / t1) * 100 Output Rise Time Output Fall Time Output-to-Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Cycle-to-Cycle Jitter PLL Lock Time REF Input Rise Time REF Input Rise Fall Time (-1, -1H) (-1H) (-1) (-1H) (-1) (-1H) 30 pF load 10 pF load Measured at 1.4 V, FOUT = 66.67 MHz < 50 MHz Measured between 0.8 V and 2.0 V Measured between 2.0 V and 0.8 V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of the device Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Measured between 0.8 V to 2.0 V Measured between 2.0 V to 0.8 V 0 0 Test Conditions Min 15 15 40 45 50 50 Typ Max 100 133.33 60 55 2.5 1.5 2.5 1.5 250 350 700 200 1.0 1.0 1.0 Unit MHz % ns ns ps ps ps ps ms ns ns
4. All parameters specified with loaded outputs.
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NB2305A
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay.
For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero-input-output delay.
SWITCHING WAVEFORMS
t1 t2 1.4 V 1.4 V 1.4 V OUTPUT 2.0 V 0.8 V t3 2.0 V 0.8 V t4 0V 3.3 V
Figure 3. Duty Cycle Timing
Figure 4. All Outputs Rise/Fall Time
OUTPUT OUTPUT
1.4 V 1.4 V t5
INPUT OUTPUT t6
V DD 2 V DD 2
Figure 5. Output - Output Skew
Figure 6. Input - Output Propagation Delay
CLKOUT, Device 1 CLKOUT, Device 2 t7
V DD 2 V DD 2
Figure 7. Device - Device Skew
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NB2305A
TEST CIRCUITS
VDD VDD 0.1 mF VDD 0.1 mF 1 kW OUTPUTS 1 kW VDD GND 0.1 mF GND GND 10 pF
OUTPUTS
CLKOUT CLOAD
VDD 0.1 mF GND
Figure 8. Test Circuit #1
Figure 9. Test Circuit #2 For parameter t8 (output slew rate) on -1H devices
ORDERING INFORMATION
Device NB2305AC1DG NB2305AC1DR2G NB2305AI1DG NB2305AI1DR2G NB2305AC1HDG NB2305AC1HDR2G NB2305AI1HDG NB2305AI1HDR2G NB2305AC1DTG NB2305AC1DTR2G NB2305AI1DTG NB2305AI1DTR2G NB2305AC1HDTG NB2305AC1HDTR2G NB2305AI1HDTG NB2305AI1HDTR2G Marking 5C1 5C1 5I1 5I1 5C1H 5C1H 5I1H 5I1H 5C1 5C1 5I1 5I1 5C1H 5C1H 5I1H 5I1H Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) Shipping 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel 100 Units / Rail 2500 Tape & Reel 100 Units / Rail 2500 Tape & Reel 100 Units / Rail 2500 Tape & Reel 100 Units / Rail 2500 Tape & Reel Availability Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB2305A
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AG
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
-X-
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB2305A
PACKAGE DIMENSIONS
TSSOP-8 CASE 948J-01 ISSUE A
K REF 0.10 (0.004)
M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
8x
0.15 (0.006) T U
S
TU
S
V
S
K
2X
L/2
8
5
L
PIN 1 IDENT. 1 4
B -U-
J J1
SECTION N-N N
0.15 (0.006) T U
S
A -V- N F
0.25 (0.010) M
DETAIL E C 0.10 (0.004) -T- SEATING
PLANE
D
G H
SEE DETAIL E
Pentium is a registered trademark of Intel Corporation. Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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K1
-W-
NB2305A/D

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